Filter
Top Products
Rev. 5.00, 09/03, page 285 of 760
Burst Write: The timing chart for a burst write is shown in figure 10.17. In the SH7709S, a burst
write occurs only in the event of cache write-back or 16-byte DMAC transfer. In a burst write
operation, following the Tr cycle in which ACTV command output is performed, a WRIT
command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-
precharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as
the write command. In case of the write with auto-precharge command, precharging of the
relevant bank is performed in the synchronous DRAM after completion of the write command,
and therefore no command can be issued for the same bank until precharging is completed.
Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is
also added as a wait interval until precharging is started following the write command. Issuance of
a new command for the same bank is deferred during this interval. The number of Trwl cycles can
be specified by the TRWL bits in MCR.