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Rev. 5.00, 09/03, page xxii of xliv
Section 10 Bus State Controller (BSC)
......................................................................... 223
10.1 Overview........................................................................................................................... 223
10.1.1 Features ................................................................................................................ 223
10.1.2 Block Diagram ..................................................................................................... 225
10.1.3 Pin Configuration ................................................................................................. 226
10.1.4 Register Configuration ......................................................................................... 228
10.1.5 Area Overview ..................................................................................................... 229
10.1.6 PCMCIA Support................................................................................................. 232
10.2 BSC Registers.................................................................................................................... 235
10.2.1 Bus Control Register 1 (BCR1)............................................................................ 235
10.2.2 Bus Control Register 2 (BCR2)............................................................................ 239
10.2.3 Wait State Control Register 1 (WCR1)................................................................ 240
10.2.4 Wait State Control Register 2 (WCR2)................................................................ 241
10.2.5 Individual Memory Control Register (MCR)....................................................... 245
10.2.6 PCMCIA Control Register (PCR)........................................................................ 248
10.2.7 Synchronous DRAM Mode Register (SDMR)..................................................... 252
10.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 253
10.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 255
10.2.10 Refresh Time Constant Register (RTCOR).......................................................... 256
10.2.11 Refresh Count Register (RFCR)........................................................................... 256
10.2.12 Cautions on Accessing Refresh Control Related Registers.................................. 257
10.2.13 MCS0 Control Register (MCSCR0)..................................................................... 258
10.2.14 MCS1 Control Register (MCSCR1)..................................................................... 259
10.2.15 MCS2 Control Register (MCSCR2)..................................................................... 259
10.2.16 MCS3 Control Register (MCSCR3)..................................................................... 259
10.2.17 MCS4 Control Register (MCSCR4)..................................................................... 259
10.2.18 MCS5 Control Register (MCSCR5)..................................................................... 259
10.2.19 MCS6 Control Register (MCSCR6)..................................................................... 259
10.2.20 MCS7 Control Register (MCSCR7)..................................................................... 259
10.3 BSC Operation .................................................................................................................. 260
10.3.1 Endian/Access Size and Data Alignment ............................................................. 260
10.3.2 Description of Areas............................................................................................. 265
10.3.3 Basic Interface...................................................................................................... 268
10.3.4 Synchronous DRAM Interface............................................................................. 276
10.3.5 Burst ROM Interface............................................................................................ 304
10.3.6 PCMCIA Interface ............................................................................................... 307
10.3.7 Waits between Access Cycles .............................................................................. 319
10.3.8 Bus Arbitration..................................................................................................... 320
10.3.9 Bus Pull-Up.......................................................................................................... 321
10.3.10 MCS[0] to MCS[7] Pin Control........................................................................... 323
Section 11 Direct Memory Access Controller (DMAC)
.......................................... 327
11.1 Overview........................................................................................................................... 327