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Rev. 5.00, 09/03, page 242 of 760
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states
inserted in physical space area 6. Also specify the number of states for burst transfer.
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Bit 15:
A6W2
Bit 14:
A6W1
Bit 13:
A6W0
Inserted
Wait States W
WW
WA
AA
AI
II
IT
TT
T Pin
Number of States
Per Data Transfer W
WW
WA
AA
AI
II
IT
TT
T Pin
0 0 0 0 Disabled 2 Enabled
1 1 Enabled 2 Enabled
1 0 2 Enabled 3 Enabled
1 3 Enabled 4 Enabled
1 0 0 4 Enabled 4 Enabled
1 6 Enabled 6 Enabled
1 0 8 Enabled 8 Enabled
110
(Initial value)
Enabled 10 Enabled
Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states
inserted in physical space area 5. Also specify the number of states for burst transfer.
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Bit 12:
A5W2
Bit 11:
A5W1
Bit 10:
A5W0
Inserted
Wait States W
WW
WA
AA
AI
II
IT
TT
T Pin
Number of States
Per Data Transfer W
WW
WA
AA
AI
II
IT
TT
T Pin
0 0 0 0 Disabled 2 Enabled
1 1 Enabled 2 Enabled
1 0 2 Enabled 3 Enabled
1 3 Enabled 4 Enabled
1 0 0 4 Enabled 4 Enabled
1 6 Enabled 6 Enabled
1 0 8 Enabled 8 Enabled
110
(Initial value)
Enabled 10 Enabled