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Rev. 5.00, 09/03, page 98 of 760
• Illegal slot instruction
Conditions:
a. When undefined code in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
b. When an instruction that rewrites PC in a delay slot is decoded
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
c. When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not apply.
Operations: PC of the immediately preceding delay branch instruction is saved to SPC. SR
of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT.
The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
When an undefined instruction other than H'Fxxx is decoded, operation cannot be
guaranteed.
• User break point trap
Conditions: When a break condition set in the user break controller is satisfied
Operations: When a post-execution break occurs, PC of the instruction immediately after
the instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of
the instruction that set the break point is set in SPC. SR when the break occurs is set in
SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch
occurs to PC = VBR + H'0100. See section 7, User Break Controller, for more information.
• DMA address error
Conditions:
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
Operations: PC of the instruction immediately after the instruction executed before the
exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is
set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC =
VBR + H'0100.