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Rev. 5.00, 09/03, page 343 of 760
11.2.5 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the
DMAC transfer mode.
These register values are initialized to 0 in a reset. The previous value is retained in standby mode.
Bit: 15 14 13 12 11 10 9 8
——————PR1PR0
Initial value:00000000
R/W:RRRRRRR/WR/W
Bit:76543210
—————AENMIFDME
Initial value:00000000
R/W:RRRRRR/(W)
*
R/(W)
*
R/W
Note: * Only 0 can be written to the AE and NMIF bits after 1 is read.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 9 and 8—Priority Mode Bits 1 and 0 (PR1, PR0): Select the priority level between
channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1 Bit 8: PR0 Description
0 0 CH0 > CH1 > CH2 > CH3 (Initial value)
0 1 CH0 > CH2 > CH3 > CH1
1 0 CH2 > CH0 > CH1 > CH3
1 1 Round-robin
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.