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Rev. 5.00, 09/03, page 179 of 760
7.3.8 Notes
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
a. A condition match occurs when B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which an A-channel match and a channel B match
occur simultaneously, is set.
b. Since the CPU has a pipeline configuration, the pipeline determines the order of an
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
c. When the bus cycle condition for channel A is specified as a break before execution
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
are read.
6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
follows:
a. Break and instruction fetch exceptions: Instruction fetch exception occurs first.
b. Break before execution and operand exception: Break before execution occurs first.
c. Break after execution and operand exception: Operand exception occurs first.