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Rev. 5.00, 09/03, page 154 of 760
7.2.3 Break Bus Cycle Register A (BBRA)
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A. A power-on reset initializes BBRA to H'0000.
Bit: 15 14 13 12 11 10 9 8
————————
Initial value:00000000
R/W:RRRRRRRR
Bit:76543210
CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1 Bit 6: CDA0 Description
0 0 Condition comparison is not performed (Initial value)
* 1 The break condition is the CPU cycle
1 0 The break condition is the DMAC cycle
*: Don’t care
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 5: IDA1 Bit 4: IDA0 Description
0 0 Condition comparison is not performed (Initial value)
1 The break condition is the instruction fetch cycle
1 0 The break condition is the data access cycle
1 The break condition is the instruction fetch cycle or data access
cycle