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Rev. 5.00, 09/03, page 367 of 760
CKIO
DRAK
(High output)
Bus cycle
DREQ
DACK
(RD output)
DMAC(W)
CPU
DMAC(W)
DMAC(R)
CPU
1st sampling 2nd sampling 3rd sampling
Figure 11.17 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:
4 Cycles)