Filter
Top Products
Rev. 5.00, 09/03, page xxxi of xliv
Figures
Figure 1.1 Block Diagram ..................................................................................................... 6
Figure 1.2 Pin Assignment (FP-208C, FP-208E) .................................................................. 7
Figure 1.3 Pin Assignment (BP-240A).................................................................................. 8
Figure 2.1 User Mode Register Configuration ...................................................................... 20
Figure 2.2 Privileged Mode Register Configuration.............................................................. 21
Figure 2.3 General Registers ................................................................................................. 22
Figure 2.4 System Registers .................................................................................................. 23
Figure 2.5 Register Set Overview, Control Registers............................................................ 24
Figure 2.6 Longword............................................................................................................. 25
Figure 2.7 Data Format in Memory....................................................................................... 25
Figure 2.8 Processor State Transitions................................................................................... 54
Figure 3.1 MMU Functions................................................................................................... 57
Figure 3.2 Virtual Address Space Mapping........................................................................... 59
Figure 3.3 MMU Register Contents ...................................................................................... 62
Figure 3.4 Overall Configuration of the TLB........................................................................ 63
Figure 3.5 Virtual Address and TLB Structure...................................................................... 64
Figure 3.6 TLB Indexing (IX = 1)......................................................................................... 65
Figure 3.7 TLB Indexing (IX = 0)......................................................................................... 66
Figure 3.8 Objects of Address Comparison........................................................................... 67
Figure 3.9 Operation of LDTLB Instruction.......................................................................... 71
Figure 3.10 Synonym Problem................................................................................................ 73
Figure 3.11 MMU Exception Generation Flowchart............................................................... 78
Figure 3.12 MMU Exception Signals in Instruction Fetch...................................................... 79
Figure 3.13 MMU Exception Signals in Data Access ............................................................. 80
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access........................ 82
Figure 4.1 Vector Table......................................................................................................... 86
Figure 4.2 Example of Acceptance Order of General Exceptions......................................... 89
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers......... 92
Figure 5.1 Cache Structure.................................................................................................... 104
Figure 5.2 CCR Register Configuration ................................................................................ 106
Figure 5.3 CCR2 Register Configuration .............................................................................. 107
Figure 5.4 Cache Search Scheme (Normal Mode) ................................................................ 110
Figure 5.5 Write-Back Buffer Configuration......................................................................... 112
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access...................... 114
Figure 6.1 Block Diagram of INTC....................................................................................... 118
Figure 6.2 Example of IRL Interrupt Connection.................................................................. 122
Figure 6.3 Interrupt Operation Flowchart.............................................................................. 144
Figure 6.4 Example of Pipeline Operations when IRL Interrupt is Accepted ....................... 148
Figure 7.1 Block Diagram of User Break Controller............................................................. 150
Figure 8.1 Canceling Standby Mode with STBCR.STBY..................................................... 189
Figure 8.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output......................... 192