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Rev. 5.00, 09/03, page 689 of 760
CKIO
A
12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A
25 to A16
A
15 to A0
Tnop
Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4
D31 to D0
t
AD
t
AD
t
CSD3
t
CSD3
t
RWD
t
RWD
t
RASD2
t
DQMD
t
DQMD
t
BSD
t
BSD
(High)
t
AD
t
AD
t
AD
t
RDS2
t
RDH2
t
RDS2
t
RDH2
t
CASD2
t
CASD2
t
AD
Row address
Read command
Column address
t
DAKD1
t
DAKD1
DACKn
Figure 23.30 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 1)