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Rev. 5.00, 09/03, page 359 of 760
CKIO
A25 to A0
D31 to D0
RD
WEn
DACKn
CSn
Transfer
source address
+4 +8 +12
Figure 11.11 Example of DMA Transfer Timing in Single Address Mode
(16-byte Transfer, External Memory Space (Ordinary Memory) →
→→
→ External Device with
DACK)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of
CHCR0–CHCR3.
• Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (byte,
word, longword, or 16-byte unit) DMAC. When another transfer request occurs, the bus is
obtained from the other bus master and transfer is performed for one transfer unit. When that
transfer ends, the bus is passed to the other bus master. This is repeated until the transfer end
conditions are satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of the transfer request source,
transfer source, and transfer destination settings. Figure 11.12 shows an example of DMA
transfer timing in cycle-steal mode. Transfer conditions shown in the figure are:
Dual address mode
DREQ level detection