Filter
Top Products
Rev. 5.00, 09/03, page 668 of 760
EXTAL input
or CKIO
input
Stable input clock
Reset or NMI interrupt request
Stable input clock
Normal NormalStandby
PLL output,
CKIO output
Internal clock
STATUS 0
STATUS 1
PLL synchronization
Note: PLL oscillation settling time during the continued oscillation mode or
when clock is input from EXTAL pin or CKIO pin
t
PLL1
PLL synchronization
Figure 23.8 PLL Synchronization Settling Time during Standby Recovery (Reset or NMI)
EXTAL input
or CKIO input
Stable input clock
IRQ4 – IRQ0/IRL3 – IRL0 interrupt request
Stable input clock
Normal Normal
PLL output,
CKIO output
Internal clock
STATUS 0
STATUS 1
Note: PLL oscillation settling time
during the continued oscillation mode or
when clock is input from EXTAL pin or CKIO pin
t
PLL1
PLL synchronization
Standby
PLL synchronization
t
IRLSTB
Figure 23.9 PLL Synchronization Settling Time during Standby Recovery
(IRQ/IRL or PINT0/PINT1 Interrupt)