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Appendix A: Memory and Register Mapping
A-18
AM700 Audio Measurement Set Service Manual
This explanation assumes a transfer of eight words from DSP local memory
address AS0 to shared memory address AD0
Count # = # of word transfer – 1
DSP instruction access address = AD0
DMA Source address =
AS0+1 DMA Destination address = AD0+1
* # of word(s) transfer must be equal to factor of four words.
1. DSP Write Access: Address:Destination Start Address(DSA0)
DSA0 → DSW0
a. DMA Interface(DI) stored the DSA0 in address buffer
b. DI stored DSW0 DMA WRITE BUFFER
c. generated DMA Trigger (IRQB)
2. DMA Write Access: DSA1 → DSW1
a. DI stored DSW1 DMA WRITE BUFFER
b. generated DMA Trigger (IRQB)
3. DMA Write Access: DSA2 → DSW2
a. DI stored DSW2 DMA WRITE BUFFER
b. generated DMA Trigger (IRQB)
4. DMA Write Access: DSA3 → DSW3
a. DI stored DSW3 DMA WRITE BUFFER
b. generated DMABR
c. If DMABG asserted, write 4 long words to DRAM
d. generated DMA Trigger (IRQB)
5. DMA Write Access:Address:Destination Start Address(DSA4)
DSA4 → DSW4
a. DMA Interface(DI) stored the DSA4 in address buffer
b. DI stored DSW5 DMA WRITE BUFFER
c. generated DMA Trigger (IRQB)
DMA WRITE Procedure