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Theory of Operation
AM700 Audio Measurement Set Service Manual
3–21
H Source Selection. A solid-state FET switch selects the source of the AES
reference signal from either the AES Ref input or, when the main input
selection is From Generator, the Reference output.
H The decoded data is applied to the DSP through the Data Formatter and
Sample Transmitter just as for the main audio signal.
DSP Mode. The DSP Mode overrides the normal (AES) mode generator. Control
of the main output is disabled. DSP mode provides a direct I/O path to the
Digital Audio board DSP through the DSP port connector.
The DSP mode requires an external clock. If an external clock is not present in
DSP mode, then all control and measurement of the interface parameters is
suspended until returning to the AES mode.
Digital Signal Processor (diagram 1)
The following portion of the Digital Audio board circuit descriptions follows the
layout of the schematic diagrams. Some information will be duplicated from the
previous discussion, but is included again with references to the circuit sche-
matic diagrams.. The Digital Audio board is composed of the Digital Signal
Processor, the Digital Generator, and the Digital Receiver. A simplified block
diagram of the DSP part of the digital audio board was shown previously in
Figure 3–6. In the DSP board circuitry, there are local registers, an analog
interface port, a DMA interface, and fast static memories that reside on the port
A and port B processor buses. Refer to schematic diagram 1 of the A3 circuit
board for the following DSP circuit description.
The DSP circuitry on diagram 1 is composed of the DSP chip, U4, address
decoder U5, random-access memory SIMM U98, and the host interface buffers,
U99 and U100.
The DSP chip, U4, is a 24-bit general purpose digital signal processor. Physical-
ly, it is a 132 pin flat-pack integrated circuit. It has a host interface for commu-
nications with the CPU of the AM700, a synchronous serial interface, a 24-pin
data bus, a 16-pin address bus, and control pins for handling bus control and
interrupts. The DSP also has an on-board phase-lock loop (PLL) circuit.
DSP Data and Address Buses. The data and address buses of the DSP provide
access to external memory and other devices on the DSP bus. The address
decoder, U5, provides the required chip selects so the DSP can address individu-
al devices on the common bus. There are no other controlling devices on the data
bus of the DSP so no provisions are needed to grant bus control away from the
DSP.
Digital Audio Board DSP