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9–18
AM700 Audio Measurement Set Service Manual
DSP
Port A Memory
RX ASIC
4
CKCPU
CPU CK
DSP RST
RST40
CPU RST
CPU RST
RSTH
Master Reset
RX ASIC
AN1[0 – 3]
AN0[0 – 3]
DA[0 – 31]
CHIP[0 – 7]
DIC[0 – 31]
BA[0 – 31]
BA[0 – 31]
BD[0 – 31]
BD[0 – 31]
3
3
3
AND
SERX0
SERX1
IRQC
IRQA
5
LADR[0 – 31]
Digital Data
Analog Data
3
RSTL RSTL
IRQB
IRQB
Port A Port B
2
2
3
3
3
ADRA[0 – 31]
2
2
Serial
Audio Data
to
Front Panel
via
CPU Board
Bus
Arbitration
Control PAL
Program
Register
Status
Register
Audio
Serializer
Board Registers,
Bus Arbitrator and
Serializer
Analog Port
Control
Digital
Signal
Processor
Version
PAL
Interrupt
Register
Clock
Oscillator
Clock
Generator
System
Reset
DSP
Clocks
Reset and
Clocks
Sample
Receiver
B Memory Control
Port B
Memory
DSP/CPU Interface
ASIC
Data
Bus
Buffers
Clock
Driver
Address
Bus
Registers
Address
Decoder
Bus Buffer
and
Connectors
CPU
CPU
Figure 9–14: DSP block diagram