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Theory of Operation
AM700 Audio Measurement Set Service Manual
3–27
The decoupling capacitors associated with the +5 V power to the various devices
on the Digital Audio board are also shown in this diagram. The +5 V power to
this board is fused by F3, a 2 A fuse. All of the input power lines are provided
with additional decoupling circuits (LC filters) near the power supply connector,
J30.
Decoders (diagram 9)
The Decoder circuitry contain the Main and Reference Decoders, the AES
Reference Generator, and the Timing Generator.
The Main and Reference Decoders accept the serial data streams and decode the
preambles to output the clock signals used to clock the serial data through the
Sample Transmitter. The left and right data samples are both on the serial data
line to the DSP. The word clock is a square-wave signal that is high for left
channel data and low for right channel data. The data is separated later by the
DSP.
The Reference Generator receives timing signals and produces an output that is
encoded as a valid AES Reference signal. The + and – AES REF OUT signals
are available at the rear panel AES REF connectors.
A separate Timing Generator circuit is a PAL that accepts various inputs
including the ACQ clock, a TTL-level clock signal, and generates various timing
signal to other portions of the Digital Audio board.
Serial Control (diagram 10)
Control signals throughout the Digital Audio board are developed in the Serial
Control circuitry. The DSP writes control data to the Serial ID PAL. This PAL
outputs a stream of serial data that defines the control states to be set. This data
loaded into a chain of serial in/parallel out registers that hold the control data bits
between updates. The last carry out of the register is applied to the Serial Status
registers which provide read back path. Also applied to these Serial Status
registers is the status outputs of both the Main and the Reference Decoders. The
status of the decoders then may be read back for input to the DSP through the
Serial ID PAL.