Filter
Top Products
Appendix A: Memory and Register Mapping
AM700 Audio Measurement Set Service Manual
A-17
3. DMA Read Access: SSA2 → SSW1
DMA Write Access: DSA1 ← SSW1
a. generated DMA Trigger (IRQB)
4. DMA Read Access: SSA3 → SSW2
DMA Write Access: DSA2 ← SSW2
a. generated DMA Trigger (IRQB)
5. DMA Read Access: SSA4 → SSW3
DMA Write Access: DSA3 ← SSW3
a. DMA Interface (DI) stored the SSA4 and generated bus request
(DMABR)
b. Wait for Bus Grant (DMABG)
c. If DMABG asserted, store 4 long words into DMA READ buffer
d. generated DMA Trigger (IRQB)
6. DMA Read Access: SSA5 → SSW4
DMA Write Access: DSA4 ← SSW4
a. generated DMA Trigger (IRQB)
7. DMA Read Access: SSA6 → SSW5
DMA Write Access: DSA5 ← SSW5
a. generated DMA Trigger (IRQB)
8. DMA Read Access: SSA7 → SSW6
DMA Write Access: DSA6 ← SSW6
a. generated DMA Trigger (IRQB)
9. DMA Read Access: SSA8 → SSW7
DMA Write Access: DSA7 ← SSW7
a. DMA Interface (DI) stored the SSA8 and generated bus request
(DMABR)
b. Wait for Bus Grant (DMABG)
c. If DMABG asserted, store 4 long words into DMA READ buffer
d. generated DMA Trigger (IRQB)
10. DSP Write to DMA Reset Register (DRR) to stop the process.