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Theory of Operation
3–48
AM700 Audio Measurement Set Service Manual
Circuit blocks affected by the power up reset or manual reset are:
H DRAM error detection outputs are masked during and after the reset is
deasserted,
H DRAM parity is set to even during and after the reset is deasserted, NVRAM
is write protected during and after the reset is deasserted,
H FEPROM is write protected during and after the reset is deasserted,
H All interrupt signals (level 7 – level 1) are masked during and after the reset
is deasserted, DSP96002 is in reset state during and after the reset is
deasserted,
H MC68040 is in reset state during the time reset is active low, Broad Program
Register(BPR) is reset during and after the reset is deasserted,
H Time-Out status bit is masked during and after the reset is deasserted. Circuit
blocks affected by the Host CPU software reset are: DRAM error detection
outputs are masked during and after the reset is deasserted,
H DRAM parity is set to even during and after the reset is deasserted,
.NVRAM is write protected during and after the reset is deasserted,
H FEPROM is write protected during and after the reset is deasserted,
H All interrupt signals (level 7 – level 1) are masked during and after the reset
is deasserted. The DSP (96002) is in reset state during and after the reset is
deasserted and the Broad Program Register (BPR) is reset during and after
the reset is deasserted.
Pressing the reset button resets both processors and their peripherals.
There is a free running 32-bit counter resident in the host CPU bus. It is a read
only counter. The wrap around time is approx. 19.4 min. The address to the
counter is $50000000.
Four address lines, QADS24 through QADS27, are applied to U79, a 4-to-16
line decoder/demultiplexor, for decoding. Twelve outputs are used as chip selects
and read or write enables. The remaining four outputs are not used. Those same
address lines plus QADS28 through QADS31 are applied to U128 for decoding
into additional chip selects and control signals.
Manual System Reset
Counter
Address Decoder