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Appendix A: Memory and Register Mapping
A-12
AM700 Audio Measurement Set Service Manual
Table A-18: DUARTB register addresses
Register address Read Write
$11000000 Mode Register A (MR1A, MR2A) Mode Register A (MR1A, MR2A)
$11000004 Status Register A (SRA) Clock Select Register A (CSRA)
$11000008 Do Not Access Command Register A (CRA)
$1100000C Receiver Buffer A (RBA) Transmitter Buffer A (TBA)
$11000010 Input Port Change Register (IPCR) Auxiliary Control Register (ACR)
$11000014 Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
$11000018 Counter Mode:Current MSB of
Counter (CUR)
Counter/Timer Upper Register
(CTUR)
$1100001C Counter Mode:Current LSB of
Counter (CLR)
Counter/Timer Lower Register
(CTLR)
$11000020 Mode Register B (MR1B, MR2B) Mode Register B (MR1B, MR2B)
$11000024 Status Register B (SRB) Clock Select Register B (CSRB)
$11000028 Do Not Access Command Register B (CRB)
$1100002C Receiver Buffer B (RBB) Transmitter Buffer B (TBB)
$11000030 Interrupt Vector Register (IVR) Interrupt Vector Register (IVB)
$11000034 Input Port (Unlatched) Output Port Configuration Reg
(OPCR)
$11000038 Start Counter Command Output Port Reg (OPR) Bit Set
Command
$1100003C Stop Counter Command Output Port Reg (OPR) Bit Reset
Command
Table A-19: UART port B output port register
Bit name Description
OP1 Keyboard Clock Inhibit
Logic “1” : Clock Inhibited (lowering the “clock” line to a logic “0”)
Logic “0” : Clock Enabled (clock line is logic “1”)
OP4 Receiver Clock Enable/data receive inhibit
Logic “1” : Receive Clock inhibited
Logic “0” : Receive Clock enabled
OP6 Data Transmit Ready
Logic “1” : Data transmit inhibit (or Data transmit not ready)
Logic “0” : Data is ready to transmit