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Intel® PXA255 Processor Developer’s Manual 2-27
System Architecture
0x4060_0068 UBCR2 UDC Byte Count Register 2
0x4060_006C UBCR4 UDC Byte Count Register 4
0x4060_0070 UBCR7 UDC Byte Count Register 7
0x4060_0074 UBCR9 UDC Byte Count Register 9
0x4060_0078 UBCR12 UDC Byte Count Register 12
0x4060_007C UBCR14 UDC Byte Count Register 14
0x4060_0080 UDDR0 UDC Endpoint 0 Data Register
0x4060_0100 UDDR1 UDC Endpoint 1 Data Register
0x4060_0180 UDDR2 UDC Endpoint 2 Data Register
0x4060_0200 UDDR3 UDC Endpoint 3 Data Register
0x4060_0400 UDDR4 UDC Endpoint 4 Data Register
0x4060_00A0 UDDR5 UDC Endpoint 5 Data Register
0x4060_0600 UDDR6 UDC Endpoint 6 Data Register
0x4060_0680 UDDR7 UDC Endpoint 7 Data Register
0x4060_0700 UDDR8 UDC Endpoint 8 Data Register
0x4060_0900 UDDR9 UDC Endpoint 9 Data Register
0x4060_00C0 UDDR10 UDC Endpoint 10 Data Register
0x4060_0B00 UDDR11 UDC Endpoint 11 Data Register
0x4060_0B80 UDDR12 UDC Endpoint 12 Data Register
0x4060_0C00 UDDR13 UDC Endpoint 13 Data Register
0x4060_0E00 UDDR14 UDC Endpoint 14 Data Register
0x4060_00E0 UDDR15 UDC Endpoint 15 Data Register
0x4060_0050 UICR0 UDC Interrupt Control Register 0
0x4060_0054 UICR1 UDC Interrupt Control Register 1
0x4060_0058 USIR0 UDC Status Interrupt Register 0
0x4060_005C USIR1 UDC Status Interrupt Register 1
Standard
UART
0x4070_0000
0x4070_0000 STRBR Receive Buffer Register (read only)
0x4070_0000 STTHR Transmit Holding Register (write only)
0x4070_0004 STIER Interrupt Enable Register (read/write)
0x4070_0008 STIIR Interrupt ID Register (read only)
0x4070_0008 STFCR FIFO Control Register (write only)
0x4070_000C STLCR Line Control Register (read/write)
0x4070_0010 STMCR Modem Control Register (read/write)
0x4070_0014 STLSR Line Status Register (read only)
0x4070_0018 STMSR Reserved
0x4070_001C STSPR Scratch Pad Register (read/write)
0x4070_0020 STISR Infrared Selection Register (read/write)
0x4070_0000 STDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4070_0004 STDLH Divisor Latch High Register (DLAB = 1) (read/write)
Table 2-8. System Architecture Register Address Summary (Sheet 7 of 12)
Unit Address Register Symbol Register Description