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Intel® PXA255 Processor Developer’s Manual 6-65
Memory Controller
When writes goes to a card sockets and a byte has been masked via an internal byte enable, the
write does not occur on the external bus. For reads, one half-word is always read from the socket,
even if only 1 byte is requested. In some cases, based on internal address alignment, one word is
read, even if only 1 byte is requested.
All DMA modes are supported in the Card interface increment the address.
Table 6-31. Common Memory Space Write Commands
nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0]
0 0 0 1 0 Odd Byte Even Byte
10010 Unimportant Even Byte
1 0 1 1 0 Unimportant Odd Byte
Table 6-32. Common Memory Space Read Commands
nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0]
0 0 0 0 1 Odd Byte Even Byte
Table 6-33. Attribute Memory Space Write Commands
nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0]
00010 Unimportant Even Byte
10010 Unimportant Even Byte
1 0 1 1 0 Unimportant Unimportant
Table 6-34. Attribute Memory Space Read Commands
nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0]
00001 Unimportant Even Byte
Table 6-35. 16-Bit I/O Space Write Commands (nIOIS16 = 0)
nPCE2 nPCE1 MA<0> nPIOR nPIOW MD[15:8] MD[7:0]
00010 Odd Byte Even Byte
10010 Unimportant Even Byte
1 0 1 1 0 Unimportant Odd Byte
Table 6-36. 16-Bit I/O Space Read Commands (nIOIS16 = 0)
nPCE2 nPCE1 MA<0> nPIOR nPIOW MD[15:8] MD[7:0]
00001 Odd Byte Even Byte