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4-34 Intel® PXA255 Processor Developer’s Manual
System Integration Unit
bring the HZ output frequency down to the proper value. Since the trimming procedure is
performed every 1023 (2
10
-1) seconds, the trim must be set to delete 941.16 clocks every 1023
seconds (.92 x 1023 = 941.16). Load the counter with the hexadecimal equivalent of 941, or
0x3AD. The fractional component of this value cannot be trimmed out and constitutes the error in
trimming, described below.
This trim setting leaves an error of. 16 cycles per 1023 seconds. The error calculation yields (in
parts-per-million or ppm):
4.3.3.2.3 Maximum Error Calculation Versus RTC Accuracy
As seen from trim example #2, the maximum possible error approaches 1 clock per 2
10
-1 seconds.
Calculating the ppm error for this scenario yields:
To maintain an accuracy of +/- 5 seconds per month, the required accuracy is calculated to be:
This calculation indicates that the HZ clock output can be made very accurate through the use of
the trim procedure. Likewise, use the trim procedure to compensate for a range of factors that can
affect crystal oscillators. Such factors can include, but are not limited to:
• Manufacturing and supplier variance in the crystals
• Crystal aging effects
• System voltage differences
• System manufacturing variance
The trim procedure can counteract these factors by providing a highly accurate mechanism to
remove the variance and shifts from the manufacturing and static environment variables on an
individual system level. However, since this is a calibration solution, it is not a practical solution
for dynamic changes in the system and environment and can most likely only be done in a factory
setting due to the equipment required.
4.4 Operating System (OS) Timer
The processor contains a 32-bit OS timer that is clocked by the 3.6864 MHz oscillator. The
Operating System Count register (OSCR) is a free running up-counter. The OS timer also contains
four 32-bit match registers (OSMR3, OSMR2, OSMR1, OSMR0). Developers can read and write
to each register. When the value in the OSCR is equal to the value within any of the match
registers, and the interrupt enable bit is set, the corresponding bit in the OSSR is set. These bits are
Error
0.16 cycles
1023 sec
---------------------------
X
1 sec
32768 cycles
------------------------------- 0.002 ppm==
Error (maximum)
1 cycle
1023 sec
---------------------
X
1 sec
32768 cycles
---------------------------------- 0. 0 3 p p m==
Error
5 sec
month
---------------
X
1 month
2592000 sec
------------------------------ 1.9 ppm==