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2-26 Intel® PXA255 Processor Developer’s Manual
System Architecture
0x4050_0114 — Reserved
0x4050_0118 MISR Modem In Status Register
0x4050_011C
through
0x4050_013C
— Reserved
0x4050_0140 MODR Modem FIFO Data Register
0x4050_0144
through
0x4050_01FC
— Reserved
0x4050_0200
through
0x4050_02FC
— Primary Audio CODEC registers
0x4050_0300
through
0x4050_03FC
— Secondary Audio CODEC registers
0x4050_0400
through
0x4050_04FC
— Primary Modem CODEC registers
0x4050_0500
through
0x4050_05FC
— Secondary Modem CODEC registers
UDC 0x4060_0000
0x4060_0000 UDCCR UDC Control Register
0x4060_0008 UDCCFR UDC Control Function Register
0x4060_0010 UDCCS0 UDC Endpoint 0 Control/Status Register
0x4060_0014 UDCCS1 UDC Endpoint 1 (IN) Control/Status Register
0x4060_0018 UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register
0x4060_001C UDCCS3 UDC Endpoint 3 (IN) Control/Status Register
0x4060_0020 UDCCS4 UDC Endpoint 4 (OUT) Control/Status Register
0x4060_0024 UDCCS5 UDC Endpoint 5 (Interrupt) Control/Status Register
0x4060_0028 UDCCS6 UDC Endpoint 6 (IN) Control/Status Register
0x4060_002C UDCCS7 UDC Endpoint 7 (OUT) Control/Status Register
0x4060_0030 UDCCS8 UDC Endpoint 8 (IN) Control/Status Register
0x4060_0034 UDCCS9 UDC Endpoint 9 (OUT) Control/Status Register
0x4060_0038 UDCCS10 UDC Endpoint 10 (Interrupt) Control/Status Register
0x4060_003C UDCCS11 UDC Endpoint 11 (IN) Control/Status Register
0x4060_0040 UDCCS12 UDC Endpoint 12 (OUT) Control/Status Register
0x4060_0044 UDCCS13 UDC Endpoint 13 (IN) Control/Status Register
0x4060_0048 UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register
0x4060_004C UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register
0x4060_0060 UFNRH UDC Frame Number Register High
0x4060_0064 UFNRL UDC Frame Number Register Low
Table 2-8. System Architecture Register Address Summary (Sheet 6 of 12)
Unit Address Register Symbol Register Description