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Intel® PXA255 Processor Developer’s Manual 6-61
Memory Controller
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 6-27. MCATT0/1 Bit Definitions
0x4800_0030
0x4800_0030
MCATT0
MCATT1
Memory Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ATTx_HOLD
reserved
ATTx_ASST
ATTx_SET
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:20 — reserved
19:14
MCATTx_HO
LD
Minimum Number of memory clocks to set up address before command assertion for
MCATT for socket x is equal to MCATTx_HOLD + 2.
13:12 — reserved
11:7
MCATTx_AS
ST
Code for the command assertion time. See Table 6-29 for a description of this code and its
affects on the command assertion.
6:0
MCATTx_SE
T
Minimum Number of memory clocks to set up address before command assertion for
MCATT for socket x is equal to MCATTx_SET + 2.
Table 6-28. MCIO0/1 Bit Definitions
0x4800_0038
0x4800_003C
MCIO0
MCIO1
Memory Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IOx_HOLD
reserved
IOx_ASST IOx_SET
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:20 — reserved
19:14
MCIOx_HOL
D
Minimum Number of memory clocks to set up address before command assertion for MCIO
for socket x is equal to MCIOx_HOLD + 2.
13:12 — reserved
11:7
MCIOx_ASS
T
Code for the command assertion time. See Table 6-29 for a description of this code and its
affects on the command assertion.
6:0 MCIOx_SET
Minimum Number of memory clocks to set up address before command assertion for MCIO
for socket x is equal to MCIOx_SET + 2.