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Intel® PXA255 Processor Developer’s Manual 13-27
AC’97 Controller Unit
13.8.3.9 Mic-In Control Register (MCCR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
13.8.3.10 Mic-In Status Register (MCSR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Figure 13-9. PCM Transmit and Receive Operation
TxEntry0
TxEntry1
TxEntry2
TxEntry3
TxEntry15
31
Right Left
16 15 0
RxEntry0
RxEntry1
RxEntry2
RxEntry3
RxEntry15
31
Right Left
16 15 0
PCDR Register
31 0
Processor/DMA
TxFIFO
Written
Processor/DMA
RxFIFO
Read
PCM Transmit FIFO PCM Receive FIFO
Write
Read
Transmit Data
Receive Data
Table 13-15. MCCR Bit Definitions
Physical Address
4050_0008
MCCR Register AC’97 Controller Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:4 — reserved
3FEIE
FIFO Error Interrupt Enable (FEIE
This bit controls whether the occurrence of a receive FIFO error will cause an interrupt or
not.
0 = No interrupt will occur even if bit 4 in the MCSR is set
1 = An interrupt will occur if bit 4 in the MCSR is set.
2:0 — reserved