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6-20 Intel® PXA255 Processor Developer’s Manual
Memory Controller
1x12x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 23 ‘0’ 10 9 8 7 654321
1x12x11x32 25 24 23 22 21 20 19 18 17 16 15 14 13 25 12 ‘0’ 11 10 9 8 765432
1x12x11x16 24 23 22 21 20 19 18 17 16 15 14 13 12 24 11 ‘0’ 10 9 8 7 654321
1x13x8x32 2322212019181716151413121110 23 ‘0’ 98765432
1x13x8x16 222120191817161514131211109 22 ‘0’ 87654321
1x13x9x32 2423222120191817161514131211 24 ‘0’ 1098765432
1x13x9x16 2322212019181716151413121110 23 ‘0’ 987654321
1x13x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 ‘0’ 11 10 9 8 765432
1x13x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 ‘0’ 10 9 8 7 654321
1x13x11x32 13 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ‘0’ 11 10 9 8 765432
1x13x11x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 11 ‘0’ 10 9 8 7 654321
2x11x8x32 22212019181716151413121110 2221‘0’ 98765432
2x11x8x16 2120191817161514131211109 2120‘0’ 87654321
2x11x9x32 23222120191817161514131211 2322‘0’ 1098765432
2x11x9x16 22212019181716151413121110 2221‘0’ 987654321
2x11x10x32 24232221201918171615141312 2423‘0’111098765432
2x11x10x16 23222120191817161514131211 2322‘0’10987654321
2x11x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x11x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x12x8x32 2322212019181716151413121110 2322 ‘0’ 98765432
2x12x8x16 222120191817161514131211109 2221 ‘0’ 87654321
2x12x9x32 2423222120191817161514131211 2423 ‘0’ 1098765432
2x12x9x16 2322212019181716151413121110 2322 ‘0’ 987654321
2x12x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 ‘0’ 11 10 9 8 765432
2x12x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 ‘0’ 10 9 8 7 654321
2x12x11x32 26 25 24 23 22 21 20 19 18 17 16 15 14 13 26 25 12 ‘0’ 11 10 9 8 765432
2x12x11x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 11 ‘0’ 10 9 8 7 654321
Table 6-7. External to Internal Address Mapping for Normal Bank Addressing (Sheet 2 of 3)
# Bits
Bank x
Row x
Col x
Data
External Address pins at SDRAM RAS Time
MA<24:10>
External Address pins at SDRAM CAS Time
MA<24:10>
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10