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Intel® PXA255 Processor Developer’s Manual 4-15
System Integration Unit
4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
GEDR0, GEDR1, GEDR2, shown in Table 4-21, Table 4-22, and Table 4-23, contain a total of 85
status bits that correspond to the 85 GPIO pins. When an edge detect occurs on a pin that matches
the type of edge programmed in the GRER and/or GFER registers, the corresponding status bit is
set in GEDR. Once a GEDR bit is set by an edge event, the bit remains set until the user clears it by
writing a one to the status bit. Writing a zero to a GEDR status bit has no effect.
Each edge detect that sets the corresponding GEDR status bit for GPIO[84:0] can trigger an
interrupt request. GPIO[84:2] together form a group that can cause one interrupt request to be
triggered when any one of GEDR[84:2] are set. GPIO[0] and GPIO[1] cause independent first-
level interrupts. Refer to Section 4.2, for a description of the programming of GPIO interrupts.
Table 4-21 through Table 4-23 show the bitmaps of the GEDR0, GEDR1, and GEDR2.
Table 4-21. GEDR0 Bit Definitions
Physical Address
0x40E0_0048
GEDR0 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
ED13
ED12
ED11
ED10
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> ED[x]
GPIO Pin ‘x’ Edge Detect Status (where x= 0 through 31).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.
Table 4-22. GEDR1 Bit Definitions
Physical Address
0x40E0_004C
GEDR1 System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED63
ED62
ED61
ED60
ED59
ED58
ED57
ED56
ED55
ED54
ED53
ED52
ED51
ED50
ED49
ED48
ED47
ED46
ED45
ED44
ED43
ED42
ED41
ED40
ED39
ED38
ED37
ED36
ED35
ED34
ED33
ED32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> ED[x]
GPIO Pin ‘x’ Edge Detect Status (where x= 32 through 63).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.