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13-22 Intel® PXA255 Processor Developer’s Manual
AC’97 Controller Unit
Table 13-8. GSR Bit Definitions (Sheet 1 of 2)
Physical Address
4050_001C
GSR Register AC’97 Controller Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
CDONE
SDONE
reserved
RDCS
BIT3SLT12
BIT2SLT12
BIT1SLT12
SECRES
PRIRES
SCR
PCR
MINT
POINT
PIINT
reserved
MOINT
MIINT
GSCI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:20 — reserved
19 CDONE
Command Done (CDONE):
0 = ACUNIT has not sent command address and data to the CODEC.
1 = ACUNIT has sent command address and data to the CODEC.
This bit is cleared by software writing a ‘1’ to this location (interruptible)
18 SDONE
Status Done (SDONE):
0 = ACUNIT has not received status address and data from the CODEC.
1 = ACUNIT has received status address and data from the CODEC.
This bit is cleared by software writing a ‘1’ to this location (interruptible)
17:16 — reserved
15 RDCS
Read Completion Status:
This bit indicates the status of CODEC read completions.
0 = The CODEC read completed normally
1 = The CODEC read resulted in a timeout.
The bit remains set until cleared by software. This bit is cleared by software writing a ‘1’ to
this location.
14 BIT3SLT12
Bit 3 of slot 12:
Display Bit 3 of the most recent valid slot 12
13 BIT2SLT12
Bit 2 of slot 12:
Display Bit 2 of the most recent valid slot 12
12 BIT1SLT12
Bit 1 of slot 12:
Display Bit 1 of the most recent valid slot 12
11 SECRES
Secondary Resume Interrupt:
0 = A resume event has not occurred on the SDATA_IN_1.
1 = A resume event occurred on the SDATA_IN_1.
This bit is cleared by software writing a ‘1’ to this location (interruptible).
10 PRIRES
Primary Resume Interrupt:
0 = A resume event has not occurred on the SDATA_IN_0.
1 = A resume event occurred on the SDATA_IN_0.
This bit is cleared by software writing a ‘1’ to this location (interruptible).
9SCR
Secondary CODEC Ready (SCR)
Reflects the state of the CODEC ready bit in SDATA_IN_1 (interruptible)
8PCR
Primary CODEC Ready (PCR)
Reflects the state of the CODEC ready bit in SDATA_IN_0 (interruptible)
7MINT
Mic In Interrupt (MINT)
0 = None of the mic-in channel interrupts occurred.
1 = One of the mic-in channel interrupts occurred.
When the specific interrupt is cleared, this bit will be cleared (interruptible).