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SRCCLOCK Source Clock — This clock provides the timing for data transfer to the A5 Analog assembly’s
serial-in parallel-out shift register. This clock is generated by the A6 Digital assembly’s digital
source.
SRCDATA Source Data — This is the data line for the A5 Analog assembly’s serial-in parallel-out shift
register. This serial data line is generated by the A6 Digital assembly’s digital source.
SYSCNTR System Control — A high on this line enables the A10 Rear Panel assembly’s GPIB buffers.
This line is high when the analyzer is under GPIB control.
TRIGGER Trigger — This line changes state when the selected trigger (channel 1, channel 2, channel 3,
channel 4, or external trigger) equals or exceeds the trigger level. An active edge on this line
causes the A6 Digital assembly to trigger the analyzer.
VDATA Video Data — This is the serial data line for the external monitor. The Motherboard buffers
this line and routes three lines to the EXT MONITOR connector. Pin 3 is the data line for the
color red, pin 4 is the data line for the color green, and pin 5 is the data line for the color blue.
VSYNC Vertical Synchronization — A high on this line causes the external monitor to do a vertical
retrace. The Motherboard buffers this signal and routes it to the EXT MONITOR connector.
WEHPIBn GPIB Write Enable — A low on this line enables write operations to the A10 Rear Panel
assembly’s GPIB controller.
Agilent 35670A Voltages and Signals
A99 Motherboard
9-33