DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126
Issue 4
June 1999
Maintenance Object Repair Procedures
9-1347PROCR (RISC Processor Circuit Pack)
9
Table 9-528. TEST #895 Processor Cache Test
Error
Code
Tes t
Result Description/ Recommendation
100 ABORT The requested test did not complete within the allowable time period.
1. Retry the command.
1022
1335
2500
ABORT Internal system error
1. Retry the command.
1338 ABORT The test is not allowed to run since a planned SPE interchange is in
progress. This may be caused by a planned interchange initiated
automatically during 24 hour scheduled testing.
1. Wait 3 minutes and retry the command.
1339 ABORT The test could not run on the standby Processor circuit pack in the standby
SPE carrier because the standby SPE is unavailable.
1. Refer to “STBY-SPE” for information on why a standby SPE may be
unavailable and what repair actions should be taken. The screen for the
status spe command should indicate that handshake is down. This
may be caused by a variety of reasons such as the SPE-SELECT
switches on the DUPINT circuit packs being set to the position of the
active SPE, a failure of the DUPINT circuit pack, or loss of power on the
standby SPE. The
SPE Selected
field on the status spe screen will
display
spe a
or
spe b
if both SPE-SELECT switches are in the a or b
positions, respectively.
2000 ABORT Response to the test request was not received within the allowable time
period. If the system is equipped with the high reliability or critical reliability
configuration and if the Processor circuit pack is on the standby SPE, this
abort code may indicate that the standby SPE is not responding to the
handshake message. If this is the case, the standby SPE maintenance
software may take up to two minutes to indicate that handshake
communication with the standby SPE is down. The ABORT code will then
change to 1339 (standby SPE unavailable).
1. Retry the command at 1-minute intervals, a maximum of 3 times.
2334 ABORT The hardware mail on the standby Duplication Interface board is not ready
to receive messages.
1. Retry the command at 1-minute intervals, a maximum of 5 times.
FAIL The Processor cache is not functioning correctly.
1. Replace the Processor circuit pack immediately. To replace the
Processor circuit pack, refer to
Replacing SPE Circuit Packs
in Chapter
5.
PASS The cache portion of the Processor circuit pack is operating correctly.
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