DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126
Issue 4
June 1999
Maintenance Object Repair Procedures
9-1344PROCR (RISC Processor Circuit Pack)
9
Memory circuit packs, but part of this function is on the Processor as well. Refer
to Memory documentation for test information.
The Processor circuit pack contains a Write Buffer function that helps prevent
internal processing operations from being held up by Processor Bus activity. If
the Processor needs to write to Memory, it writes to the Write Buffer. If the
Processor Bus is in use at this time, the information is transferred to Memory at an
appropriate time. Up to 12 processor writes can be pending, waiting for transfer
to memory.
The Processor Bus contains parity checking functions. If one address or data bit
is corrupted during an access cycle, the error detection logic detects and
reports this to Processor circuit pack.
The Processor circuit pack contains interrupt and exception signals that tell the
Processor when normal or erroneous events occur in SPE components. An
example of a normal event is an interrupt that occurs when data provided by an
SPE component such as the SYSAM is available for the Processor. An example
of an error-indicating exception is detection of a parity error on the Bus when
Processor reads Memory. These types of errors result in system recovery actions
which are described in Chapter 4, ‘‘Initialization and Recovery’’
.
The Processor circuit pack contains an erasable, programmable read-only
memory (BOOTPROM) that contains the system initialization and low-level
diagnostic programs. Problems in this hardware may result in difficulties with
system start-up, restart, or SPE maintenance testing in general.
If the PBX system is equipped with High Reliability or Critical Reliability option
(i.e. with duplicated SPEs), and if a failure of the active Processor circuit pack
causes a MAJOR on-board alarm, a SPE interchange will occur if the health of
the standby SPE permits the interchange. Refer to Replacing SPE Circuit Packs
in Chapter 5 for more information about duplicated SPEs.
