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Clock Control
2-32
Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleep
generated by the IDLE instruction is partially controlled by this bit. When this
bit is cleared (default setting), the CPU Clock is stopped during the sleep, but
the MC remains running. When the idle state clock control bit is set, both the
CPU clock and the MC are stopped during sleep. Refer to section 2.12 for more
information regarding the C614’s reduced-power modes.
Note: Reference Oscillator Stopped by Programmed Disable
If the reference oscillator is stopped by a programmed disable, then, on re-
enable, the oscillator requires some time to restart and resume its correct fre-
quency. This time imposes a delay on the core processor resuming full-
speed operation. The time-delay required for the CRO to start is GREATER
than the time-delay required for the RTO to start.
2.9.4 RTO Oscillator Trim Adjustment
Bits 15 through 11 and bit 9 (6 bits total) in the ClkSpdCtrl effect a software
control for the RTO oscillator frequency. The purpose of this control is to trim
the RTO to its rated (32 kHz) specification. The correct trim value varies from
device to device. The user must program bits 15 through 11 and 9, in order to
achieve the 32-kHz specification within the rated tolerances. Texas
Instruments provides the trim value to the programmer of the P614 part with
a sticker on the body of the chip. For the C614 part, the correct trim value is
located at I/O location 0x2Fh.
RTRIM Register (Read Only) (Applies to MSP50C614 Device Only)
I/O Address 0x2Fh (17-bit wide location)
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
RRRRRRRRRRRT5T4T3T2T1T0
T: RTO oscillator-trim storage (device specific)
R: reserved for Texas Instruments use
ClkSpdCtrl Value Copied (Shaded)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T5 T4 T3 T2 T1 I T0 1 M7 M6 M5 M4 M3 M2 M1 M0
When selecting and enabling the RTO oscillator,therefore, the bits at positions
05 through 01 should be read from I/O location 0x2F (MSP50C614 device
only), then copied to the ClkSpdCtrl trim adjust (bits 15 through 11 of control
register 0x3D), and bit 0 of 0x2F I/O port should be copied to bit 9 of ClkSpdCtrl
register. The bit ordering is the same; bit 04 of I/O 0x2F copies to bit 15 of
register 0x3D. Likewise, bit 00 of I/O 0x2F copies to bit 11 of register 0x3D.