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Computation Unit
2-5
MSP50C614 Architecture
2.2 Computation Unit
The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s
algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram
of the CU is shown in Figure 2–2. The multiplier block is served by 4 system
registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand
register, a 16-bit high word product register (PH), and a 4-bit shift value register
(SV). The output of the ALU is stored in one 16-bit accumulator from among
the 32 which compose the accumulator-register block. The accumulator
register block can supply either one operand to the ALU (addressed
accumulator register or its offset register) or two operands to the ALU (both the
addressed register and its offset).
2.2.1 Multiplier
The multiplier executes a 17-bit by 17-bit 2s complement multiply and
multiply-accumulate in a single instruction cycle. The sign bit within each
operand is bit 16, and its value extends from bit 0 (LSB) to bit 15 (MSB). The
sign bit for either operand (multiplier or multiplicand) can assume a positive
value (zero) or a value equal to the MSB (bit 15). In assuming zero, the extra
bit supports unsigned multiplication. In assuming the value of bit 15, the extra
bit supports signed multiplication. Table 2–1 shows the greater magnitude
achievable when using unsigned multiplication (65535 as opposed to 32767).
Table 2–1. Signed and Unsigned Integer Representation
Unsigned Signed
Decimal Hex Decimal Hex
65535 0xFFFF −1 0xFFFF
32768 0x8000 −32768
0x8000
32767 0x7FFF 32767
0x7FFF
0
0x0000 0 0x0000
During multiplication, the lower word (LSB) of the resulting product, product
low, is multiplexed to the ALU. Product low is either loaded to or arithmetically
combined with an accumulator register. These steps are performed within the
same instruction cycle. Refer to Figure 2–3. At the end of the current execution
cycle, the upper word (MSB) of the product is latched into the product high
register (PH).