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Instruction Classification
4-27
Assembly Language Instructions
Table 4–15. Class 1b Instruction Description
C1b Mnemonic Description
0 0 0 0 OR A
n
, {
adrs
}
ORS A
n
, {
adrs
}
Logical OR the contents of the data memory location in {
adrs
}
and the selected accumulator. Result(s) stored in
accumulator(s). ALU status is modified
0 0 0 1 AND A
n
, {
adrs
}
ANDS A
n
, {
adrs
}
Logical AND the contents of the data memory location in {
adrs
}
and the accumulator. Result(s) stored in accumulator(s). ALU
status is modified
0 0 1 0 XOR A
n
, {
adrs
}
XORS A
n
, {
adrs
}
Exclusive OR the contents of the data memory location in
{
adrs
} and the accumulator. Result(s) stored in accumulator(s).
ALU status is modified
0 0 1 1 MOVB A
n
, {
adrs
}
8
MOVBS A
n
, {
adrs
}
8
Load the contents of the data memory location in {
adrs
}and to
the lower 8 bits of the accumulator. Zero fill the upper byte in the
accumulator ALU status is modified.
0 1 0 0 MOVB {
adrs
}
8
, A
n
MOVBS {
adrs
}
8
, A
n
Store the lower 8 bits of accumulator to the data memory
location in {
adrs
}. The data byte is automatically routed to either
the lower byte or upper byte in the 16 bit memory word based on
the LSB of the address. Transfer status is modified.
0 1 0 1 Reserved N/A
0 1 1 0 CMP A
n
, {
adrs
}
CMPS A
n
, {
adrs
}
Store the arithmetic status of the contents of {
adrs
} subtracted
from accumulator into the ALU status bits. The accumulator is
not modified.
0 1 1 1 MOV {
adrs
}
, *A
n
MOVS {
adrs
}
, *A
n
Look up the value stored in program memory addressed by the
accumulator and store in the data memory location in {
adrs
}.
Transfer status is modified .
1 0 0 0 MULTPL A
n
, {
adrs
}
MULTPLS A
n
, {
adrs
}
Multiply the MR register by the contents of {
adrs
} and transfer
the lower 16 bits of the result to the accumulator. Latch the
upper 16 bits into the PH register. ALU status is modified.
1 0 0 1 MOVSPH A
n
, MR, {
adrs
}
MOVSPHS A
n
, MR, {
adrs
}
Load the MR register in signed mode from the data memory
location in {
adrs
}. In parallel, subtract the PH register from the
accumulator. The string bit will string with the previous ALU
status (CF, ZF) but it will not load the string counter (executes
once). ALU status is modified.
1 0 1 0 MOVAPH A
n
, MR, {
adrs
}
MOVAPHS A
n
, MR, {
adrs
}
Load the MR register in signed mode from the data memory
location in {
adrs
}. In parallel, add the PH register to the
accumulator. The string bit will string with the previous ALU
status (CF, ZF) but it will not load the string counter (executes
once). ALU status is modified.