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Architecture
B-3
MSP50C604 Preliminary Data
B.3.1 RAM
The MSP50C604 (like MSP50C614) has 640 17–bit words of internal data
memory (static RAM). This RAM occupies a space extending from 0 to 0x27F
in the address space.
B.3.2 ROM
The MSP50C604 contains 32K by 17-bit words of internal program ROM. The
program ROM space is divided into two areas:
1) The initial 2K words of ROM (0x0000 – 0x07FF) is reserved for built in self-
test (BIST) that is provided by Texas Instruments during mass production.
2) Customer can use the ROM from address extending from 0x0800 to
0x7FFF. Restrictions on using certain program ROM location is shown in
Figure B–2.
B.3.3 I/O Pins
The MSP50C604 has 14 output pins. There are two different configurations for
these pins, host mode, and slave mode.
In
host
mode, 6 of the 14 pins are the same as pins PD0 to PD5 on port D of
the MSP50C614. The other 8 pins are the same as one of I/O port C. All of the
functions of port D on the MSP50C614 are available on the MSP50C604, in-
cluding four interrupts, the conditional branch control and the comparator.
In
slave
mode, only PD4 and PD5 are be available for general purpose I/O in-
cluding two interrupts and the comparator. PD0, PD1, PD2, and PD3, are used
to control the slave mode interface internally, and becomes INRDY
, OUTRDY,
STROBE, and R/(WZ) on the I/O pinout respectively. The other 8 pin port C,
becomes a data bus controlled by STROBE and R/WZ externally. Internally,
the port is used to transfer data between the core and the I/O latches.
External interrupts can be caused by transitions on the PD2, PD3, PD4, and
PD5. The interrupts associated with the D port are supported whether those
pins are programmed as inputs or as outputs.