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Instruction Classification
4-35
Assembly Language Instructions
Table 4–22. Class 4a Instruction Description
C4a Mnemonic Description
0 MOV {
adrs
}, R
x
Store R
x
register to data memory referred by addressing mode {adrs}. Modify
transfer status.
1 MOV R
x
, {
adrs
} Load R
x
with the value in data memory referred by addressing mode {adrs}.
Modify transfer status.
Table 4–23. Class 4b Instruction Description
C4b Mnemonic Description
0 0 ADDB R
x
,
imm8
Add 8 bit positive constant to R
x
register. Modify RX status.
0 1 SUBB R
x
,
imm8
Subtract 8 bit positive constant from R
x
register. Modify RX status.
1 0 MOVB R
x
,
imm8
Load R
x
with the an 8 bit positive constant. Modify RX status.
1 1 CMPB R
x
,
imm8
Store the status of the subtraction (R
x
– 8 bit positive constant) into RZF and RCF
bits of the STAT register. R
x
remains unchanged.
Table 4–24. Class 4c Instruction Description
C4c Mnemonic Description
0 0 ADD R
x
,
imm16
Add 16 bit positive constant to R
x
register. Modify RX status.
0 1 SUB R
x
,
imm16
Subtract 16 bit positive constant from R
x
register. Modify RX status.
1 0 MOV R
x
,
imm16
Load R
x
with the an 16 bit positive constant. Modify RX status.
1 1 CMP R
x
,
imm16
Store the status of the subtraction (R
x
– 16 bit positive constant) into RZF and RCF
bits of the STAT register. R
x
remains unchanged.
Table 4–25. Class 4d Instruction Description
C4d Mnemonic Description
0 0 ADD R
x
, R5 Add R5 to R
x
register, Modify RX status.
0 1 SUB R
x
, R5 Subtract R5 from R
x
register. Modify RX status.
1 0 MOV R
x
, R5 Load R
x
with R5. Modify RX status.
1 1 CMP R
x
, R5 Store the status of the subtraction (R
x
– R5) into RZF and RCF bits of the STAT
register. R
x
and R5 remain unchanged.