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Functional Description
1-5
Introduction to the MSP50C614
1.4 Functional Description
The device consists of a micro-DSP core, embedded program and data
memory, and a self-contained clock generation system. General-purpose pe-
riphery is comprised of 64 bits of partially configurable I/O.
The core processor is a general-purpose 16 bit micro-controller with DSP
capability. The basic core block includes a computational unit (CU), data
address unit, program address unit, two timers, eight level interrupt processor,
and several system and control registers. The core processor gives the P614
and C614 break-point capability in emulation.
The processor is a Harvard type for efficient DSP algorithm execution. It re-
quires separate program and data memory blocks to permit simultaneous ac-
cess. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into two areas: 1) The lower 2K words are re-
served by Texas Instruments for a built-in self-test, 2) the upper 30K is for user
program/data.
The data memory is internal static RAM. The RAM is configured in 640 17-bit
words. Both memories are designed to consume minimum power at a given
system clock and algorithm acquisition frequency.
A flexible clock generation system is included that enables the software to
control the clock over a wide frequency range. The implementation uses a
phase-locked loop (PLL) circuit that drives the processor clock at a selectable
frequency between the minimum and maximum achievable. Selectable
frequencies for the processor clock are spaced apart in 65.536-kHz steps. The
PLL clock-reference is also selectable; either a resistor-trimmed oscillator or
a crystal-referenced oscillator may be used. Internal and peripheral clock
sources are controlled separately to provide different levels of power
management (see Figure 1–2).
The peripheral consists of five 8-bit wide general-purpose I/O ports, one 8-bit
wide dedicated input port, and one 16-bit wide dedicated output port. The
bidirectional I/O can be configured under software control as either
high-impedance inputs or as totem-pole outputs. They are controlled via
addressable I/O registers. The input-only port has a programmable pullup
option (100-kΩ minimum resistance) and a dedicated service interrupt. These
features make the input port especially useful as a key-scan interface.
A simple one-bit comparator is also included in the periphery. The comparator
is enabled by a control register, and its pin access is shared with two pins in
one of the general-purpose I/O ports. Rounding out the C614 periphery is a