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Computation Unit
2-10
When writing an accumulator-referenced instruction, therefore, the working
accumulator address is stored in one of AP0 to AP3. The C614 instruction set
provides a two-bit field for all accumulator referenced instructions. The two-bit
field serves as a reference to the accumulator pointer which, in turn, stores the
address of the actual 16-bit accumulator. Some MOV instructions store the
contents of the APn directly to memory or load from memory to the APn
register. Other instructions can add or load 5-bit constants to the current APn
register contents. A full description of the C614 instruction set is given in
Chapter 4,
Instructions
.
Figure 2–5. Overview of the Arithmetic Logic Unit
Accumulator Block: 32, 16-bit registers AC(0) . . . AC(31)
Accumulator Block Pointers: 4, 5-bit registers AP(0) . . . AP(3)
The accumulator block pointers may assume values in one of two forms:
1) DIRECT REFERENCE:
0 . . . 31
AC Register #
2) INDIRECT REFERENCE: 0 . . . 15 points to: 0 . . . 15
0 . . . 15 OFFSET points to: 16 . . . 31
15 . . . 31 OFFSET points to: 0 . . . 15
– AP registers are served by a 5-bit processor for sequencing addresses or repetitive operations.
– Selection between the 4 AP’s is made in the 2-bit An field in all accumulator-referenced
instructions
2.2.2.3 String Operations
The AP registers are served by a 5-bit processor that provides efficient
sequencing of accumulator addresses. The design automates repetitive
operations like long data strings or repeated operations on a list of data.
When operating on a multiword data string, the address is copied from the AP
register to fetch the least significant word of the string. This copy is then
consecutively incremented to fetch the next n words of the string. At the
completion of the consecutive operations, the actual address stored in the AP
register is left unchanged; its value still points to the least significant location.
The AP register, therefore, is loaded and ready for the next repeatable
operation.