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Introduction
B-2
B.1 Introduction
MSP50C604 is a spin off of the core processor MSP50C614. It is targeted as
a slave device. An external microprocessor is needed to interface with
MSP50C604 in slave mode. It can also be used a stand alone device if desired.
B.2 Features
30k word ROM customer program memory
8 MHz uDSP core
2 IO pins can be used as a comparator
4 pins for synthesizer syncronization
Host read or write interrupts core
PLL clock synthesizer
Resistor trimmed oscillator or 32 kHz crystal
640 word RAM
PDM DAC w/direct speaker drive (32 ohm)
1 bit comparator with edge-detection interrupt service
(IMPORTANT: Not currently supported)
Serial scan port for in-circuit emulation/monitor/test
Host Mode
14 general-purpose I/O pins
Can generate interrupts
Slave Mode
Works as microprocessor peripheral
STROBE, R/W lines for host read/write control
INPUTREADY, OUTPUTREADY for handshake
B.3 Architecture
The MSP50C604 will use the 6xx device family core, including breakpoint ca-
pability. It has identical instruction sets and uses the same development tool.
MSP50P614 (EPROM device) is used for code development and testing. The
architecture block diagram is shown in Figure B–1.