Filter
Top Products
Clock Control
2-29
MSP50C614 Architecture
2.9 Clock Control
2.9.1 Oscillator Options
The C614 has two oscillator options available. Either option may be enabled
using the appropriate control bits in the clock speed control register
(ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3,
Clock Speed Con-
trol Register
.
The first oscillator option, called the resistor-trimmed oscillator (RTO), is useful
in low-cost applications where accuracy is less critical. This option utilizes a
single external resistor to reference and stabilize the frequency of an internal
oscillator. The oscillator is designed to run nominally at 32 kHz. It has a low V
DD
coefficient and a low temperature coefficient (refer to Appendix C). The
reference resistor is mounted externally across pins OSC
IN
and OSC
OUT
. The
RTO oscillator is insensitive to variations in the lead capacitance at these pins.
The required value of the reference resistor is 470 kΩ (1%).
The second oscillator option, CRO for crystal referenced, is a real time clock
utilizing a 32.768 kHz crystal. The crystal is mounted externally across pins
OSC
IN
and OSC
OUT
.
2.9.2 PLL Performance
A software controlled PLL multiplies the reference frequency (generated from
either RTO or CRO) by integer multiples. This higher frequency drives the
master clock which, in turn, drives the CPU clock. The master clock (MC)
drives the circuitry in the periphery sections of the C614. The CPU Clock drives
the core processor; its rate determines the overall processor speed. The multi-
plier in the PLL circuit, therefore, allows the master clock and the CPU clock
to be adjusted between their minimum and maximum values.
For either oscillator option, the reference frequency (32.768 kHz) is multiplied
by four before it is accessed by the PLL circuit. The base frequency for the PLL,
therefore, is 131.07 kHz, and the multiplier operates in increments of this base
frequency. The minimum multiplication of the base frequency is 1, and the
maximum multiplication is 256. The resulting master clock frequency, there-
fore, can be varied from a minimum of 131.07 kHz to a maximum of 33.554
MHz, in 131.07 kHz steps.
From the master clock to the CPU clock, there is a divide-by-two in frequency.
The CPU clock, therefore, can be set to run between 65.536 kHz and the maxi-
mum achievable (see Appendix C), in 65.536 kHz steps.