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138 Register-Based Programming Appendix B
:
Sample
Source/Control
Register
This register provides the bits that control the sample system. :
*WRITE BITS (Trigger Source Register) and
**READ BITS (Trigger Control Register)
bits 0-2 TTL_n 000 = TTLT0, 001 = TTLT1, 010 = TTLT2, ... , 011 = TTLT6, 111 = TTLT7.
bit 3 IN/OUT TTLTn line is: 0 = IN, 1 = OUT.
bit 4 EN_TTL 0 = disable TTLTn, 1 = enable TTLTn
bit 5 SLAVE 0 = not a slave module, 1 = slave module.
bit 6 MASTER 0 = not a master module, 1 = master module.
bit 7 SOFT TRIG software trigger: 0 = IMMediate disabled, 1 = IMMediate enabled.
bit 8 POS_NEG trigger slope: 0 = NEG, 1 = POS.
bit 9 EX_TRIG 0 = EXTernal trigger disabled, 1 = EXTernal trigger enabled and must be input
on the “Trig” pin on the front panel D-subminiature connector.
bits 10-11 SLAVING_PAIR 00 = MASTer0/SLAVe0; 01 = MASTer2/SLAVe2; 10 = MASTer4/SLAVe4;
11 = MASTer6/SLAVe6
bits 12-15 CMP1-4 0 = INTn disabled, 1 = INTn enabled; Example: a “1” in CMP2 means the level
set in the Trigger/Interrupt Level Channel 2 Register will be used as the INTernal
trigger source.
base + 3E
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write*
SW
ARM
IMM
SW
ARM
30 mS
delay
ABORT EX_
SAM
PLE
POS_
NEG
SOFT
SAM
PLE
EXT
TIME
BASE
INT
CLOCK
EN_
TTL
IN/
OUT
TTL_3 TTL_1 TTL_0
Read**
SW
ARM
IMM
SW
ARM
30 mS
delay
ABORT EX_
SAM
PLE
POS_
NEG
SOFT
SAM
PLE
EXT
TIME
BASE
INT
CLOCK
EN_
TTL
IN/
OUT
TTL_3 TTL_1 TTL_0
*WRITE BITS (Sample Source Register) and
**READ BITS (Sample Control Register)
bits 0-2 TTL_n 000 = TTLT0, 001 = TTLT1, 010 = TTLT2, ... , 011 = TTLT6, 111 = TTLT7.
bit 3 IN/OUT TTLTn line is: 0 = IN, 1 = OUT.
bit 4 EN_TTL 1 = enable TTLTn, 0 = disable TTLTn
bit 5 INT Clock 0 = disable sampling from internal clock source, 1 = sample from the internal clock
source.
bit 6 EXT
Timebase
0 = timebase is internal 10 MHz clock, 1 = timebase is external clock source you must
input on the “Time Base” pin on the front panel External Trigger Input connector.