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136 Register-Based Programming Appendix B
Trigger/Interrupt
Level Channel 4
Register
This register provides 8-bit data corrected for offset and gain in 2’s
complement format. :
Sample Period High
Byte Register
This register provides the high byte of the sample period.
Sample Period Low
Word Register
This register provides the low word (2 bytes) of the sample period.
Pre-Trigger Count
High Byte Register
Pre-trigger count is the number of readings stored before the trigger is
received. The minimum value is 0. The maximum number of readings is
the size of memory in bytes divided by 8 for the E1563 and divided by 4 for
the E1564.
base + 2E
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write* MSB-D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 GL
Read** MSB-D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 GL
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 4 Register)
bit 0 GL Greater than or Less than; “0” = >, “1” = <.
bits 15-8 D7-D0 data bits.
base + 30
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write* xxxxxxxx
Read** 00000000xxxxxxxx
base + 32
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write* xxxxxxxxxxxxxxxLSB
Read** xxxxxxxxxxxxxxxLSB
base + 34
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write undefined C5 C4 C3 C2 C1 C0
Read 0000000000C5C4C3C2C1C0