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Register-Based Programming 135Appendix B
Trigger/Interrupt
Level Channel 2
Register
This register provides 8-bit data corrected for offset and gain in 2’s
complement format. :
Trigger/Interrupt
Level Channel 3
Register
This register provides 8-bit data corrected for offset and gain in 2’s
complement format. :
base + 2A
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write*MSB-D7D6D5D4D3D2D1D00000000GL
Read**MSB-D7D6D5D4D3D2D1D00000000GL
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 2 Register)
bit 0 GL Greater than or Less than; “0” = >, “1” = <.
bits 15-8 D7-D0 data bits.
base + 2C
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write*MSB-D7D6D5D4D3D2D1D00000000GL
Read**MSB-D7D6D5D4D3D2D1D00000000GL
*WRITE/**READ BITS (Trigger/Interrupt Level Channel 3 Register)
bit 0 GL Greater than or Less than; “0” = >, “1” = <.
bits 15-8 D7-D0 data bits.