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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
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The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4-7. CAN Register Map
(1)
eCAN-A eCAN-B SIZE
REGISTER NAME DESCRIPTION
ADDRESS ADDRESS (x32)
CANME 0x6000 0x6200 1 Mailbox enable
CANMD 0x6002 0x6202 1 Mailbox direction
CANTRS 0x6004 0x6204 1 Transmit request set
CANTRR 0x6006 0x6206 1 Transmit request reset
CANTA 0x6008 0x6208 1 Transmission acknowledge
CANAA 0x600A 0x620A 1 Abort acknowledge
CANRMP 0x600C 0x620C 1 Receive message pending
CANRML 0x600E 0x620E 1 Receive message lost
CANRFP 0x6010 0x6210 1 Remote frame pending
CANGAM 0x6012 0x6212 1 Global acceptance mask
CANMC 0x6014 0x6214 1 Master control
CANBTC 0x6016 0x6216 1 Bit-timing configuration
CANES 0x6018 0x6218 1 Error and status
CANTEC 0x601A 0x621A 1 Transmit error counter
CANREC 0x601C 0x621C 1 Receive error counter
CANGIF0 0x601E 0x621E 1 Global interrupt flag 0
CANGIM 0x6020 0x6220 1 Global interrupt mask
CANGIF1 0x6022 0x6222 1 Global interrupt flag 1
CANMIM 0x6024 0x6224 1 Mailbox interrupt mask
CANMIL 0x6026 0x6226 1 Mailbox interrupt level
CANOPC 0x6028 0x6228 1 Overwrite protection control
CANTIOC 0x602A 0x622A 1 TX I/O control
CANRIOC 0x602C 0x622C 1 RX I/O control
CANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode)
CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode)
CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
72 Peripherals Copyright © 2003–2009, Texas Instruments Incorporated
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