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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
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6-9 Warm Reset ..................................................................................................................... 108
6-10 Example of Effect of Writing Into PLLCR Register ......................................................................... 109
6-11 General-Purpose Output Timing.............................................................................................. 110
6-12 Sampling Mode ................................................................................................................. 110
6-13 General-Purpose Input Timing ................................................................................................ 111
6-14 IDLE Entry and Exit Timing.................................................................................................... 112
6-15 STANDBY Entry and Exit Timing Diagram .................................................................................. 113
6-16 HALT Wake-Up Using GPIOn................................................................................................. 114
6-17 PWM Hi-Z Characteristics ..................................................................................................... 115
6-18 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 117
6-19 External Interrupt Timing....................................................................................................... 117
6-20 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 120
6-21 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 122
6-22 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 124
6-23 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 125
6-24 ADC Power-Up Control Bit Timing ........................................................................................... 126
6-25 ADC Analog Input Impedance Model ........................................................................................ 127
6-26 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 128
6-27 Simultaneous Sampling Mode Timing ....................................................................................... 129
6 List of Figures Copyright © 2003–2009, Texas Instruments Incorporated