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A23 SAMPLER (ESG-AP AND ESG DP SERIES)
44
750 MHz REFERENCE
RF
LO
IF
750 MHz BPF
750 MHz A
750 MHz B
1000 MHz
250 MHz
PROGRAMMABLE DIVIDER
(256 / M)
5 £ M £ 51
DATA
6
750MHz
14-150MHz
PHASE DETECTOR
UNLOCK
DETECTOR
DS1
PHASE DET
MIXER IF
HIGH/LOW
f
14-150MHz
IF
LO
L_CRS PLL_UNLK
MICROWAVE SAMPLER
SS
J3
YTO IN
» 2 dBm
fyo
RF
IF
LO
fyo = N x fs + fif
SAMPLER IF
30-70 MHz
where 5 £ N £ 9
80 MHz
80 MHz
VCO 600-900 MHz
ABUS
+8V
fs
600-735MHz
765-900MHz
2.93MHz STEPS
+14dBm
+6dBm
900 MHz
900 MHz
BIAS
ABUS- VCO-BIAS
TP3
VTUNE
COARSE PLL MIXER
750MHz
600-900 MHz
+13dBm
RF
-8dBm
MIXER IF
900 MHz
LPF
FRAC-N INPUT
2
P
J6
FRAC-N
IN
500-1000MHz
+5dBm
750MHz_A
FM_MODE
A/B
+6dBm
RF
-14dBm
LO
fif
Mode A
Mode B
2
YO PLL PHASE DETECTOR
SAMPLER IF
PHASE DET
TP4
YO PLL
PHASE DET
-.45V/RAD
f
2
POWER SUPPLIES
FILTER
FILTER
REG
+5V
REG
25V
REG
+8V
REG
4.5V
REG
2.5V
REG
-10V
Ref
Ref
Ref
Ref
Ref
+15V
P2-6,21
+15VF
+32V
P2-7
+25V
4K
1K
ABUS_+25V
ABUS_+ 8V
ABUS_+ 4.5V
+8V
-15VF
-10V
+4.5V
+2.5VR
+9V
P2-5,20
-15V
P2-2,17
+5.2V
P2-14,29
YO PLL INTEGRATOR
YO PLL
UNLOCK
DETECTOR
DS2
4
L_YOL_UNLK
YO_GAIN
DATA
L HOLD
ABUS
YO_PHSLK
TP5
YO Phaselock
TUNING VOLTAGE
TO YO DRIVER Bd
+2MHz/VOLT. DC
P1-2, 12
+
_
+
_
L_YOPLL_PRESET
YO_PREDAC
150MHz
DIGITAL INTERFACE
FROM MOTHERBOARD/CPU ASSY
J5-26
FROM MOTHERBOARD/CPU ASSY
J5-20
FROM MOTHERBOARD/CPU ASSY
J5-23
SERIAL I/O
INT 1
INT 2
INT 3
INT 4 (SERIAL DATA)
CLK
ENABLE/INTERRUPT
CLK
DATA
ENABLE/INTERRUPT
L_CRSPLL_UNLK
L_YOL_UNLK
NOT USED
NOT USED
CLK
SELECT
DATA
EEPROM
P2-24
P2-25
P2-11
DIGITAL
CONTROL
DATA
YO_PHSLK
ABUS_VCO_TUNE
ABUS_VCO_BIAS
ABUS_10V
ABUS_+25V
ABUS_+8V
ABUS_+4.5V
MUX
ABUS
P2-9
DATA
DAC
YO-PREDAC
J1
1GHz
IN
+6dBm
+
_
ABUS
ABUS_VCO_TUNE
TP2
.5
.5
VTUNE
TP1
PHASE
DET
+
_
+15V
HIGH/LOW
L_CRSPLL_PRETUNE
+/-1
750 MHz C
INTEGRATOR
A23 SAMPLER (ESG-AP AND ESG DP SERIES)
sk770b