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ESG-D SERIES RF BLOCK DIAGRAM
(OPTION UN7, UN8/UN9, 300)
sk7110b
ESG-D SERIES RF BLOCK DIAGRAM (OPTION UN7, UN8/UN9, 300 )
A SYNTHESIZER BOARD
2
2
d/dt
FM
Om
/
.5-1 GHz
5 MHz
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
X2
X2
f
F
LIN_AM_MOD
LIN_AM_MOD
PULSE_MOD
D REFERENCE BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
FM_MOD
FEED FORWARD AM
PLL
PLL
10 MHz BW
PULSE MOD
1 GHz PLL
10 MHz
SYNTH
1 GHz
REF
10 MHz
OUT
10 MHz PLL
E BASEBAND GENERATOR BOARD
F DATA GENERATOR BOARD
10 MHz DIG
EXT 13 MHz
EXT
I INPUT
EXT
Q INPUT
B OUTPUT BOARD
ALC
MODULATOR
DRIVER
ALC
MODULATOR
IQ MODULATOR
BURST
MODULATOR
.75-1 GHz
.0-.25 GHz
.25-4 GHz
0
90
VBLO
QUAD
.25-4 GHz
10 MHz SYNTH
CAL
VOLTAGE
CAL
VOLTAGE
I GAIN
Q GAIN
I OFFSET
Q OFFSET
LIN_BURST
LOG_BURST
1 GHz REF
50
-1V_REF
INT_ Q_MOD
INT_ I_MOD
MASTER
CLOCK-PLL
MASTER_CLK
PLL_LCK_SIG
BBG_BIT_CCK
SUB_I_CLK
DATA
GENERATION
CONTROL
BURST MOD
SWITCH &
FILTERS
CONTROL
BURST & DELAY
BURST_PLS
BURST_PULSE
BURST_ENVELOPE
BURST
MODULATOR
DRIVER
ALC
HOLD
HOLD ALC
ALC
DETECTOR
IN_BAND_AM
ALC_REF
BURST
DETECTOR
SHAPING
DAC
ALC REF
DAC
DAC
G BERT MEASURMENT BOARD
INPUT
BERT
DATA IN
BERT
CLK IN
BERT
GATE IN
BERT ASIC
BER
SYNC LOSS
BER
NO DATA
BER
ERR OUT
BER
TEST OUT
BER
MEAS END
DSP
BER
CALCULATION
RPP
C ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
DAC
DAC
DAC
DAC
DAC
DAC
AUX
OUT
(COHERENT
CARRIER)
DATA_CLOCK
EVENT 1
PATTERN
TRIGGER
EVENT 2
USER_DATA_EN
EVENT1_OUT
DATA
EXT_BURST
EXT_SYNC
GLOBAL CLOCK INPUTS
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN8=1M
UN8&UN9=8M
MPU
FPGA
FPGA
FPGA
MPU BUS
FPGA BUS
BASEBAND
GEN. I/O
OPTION 300
DEMODULATOR
DAC
IF
ADC
FPGA
CLK
CLK
DSP
INTERFACE
SWITCH
DOWN CONVERTER
FPGA
MEMORY
PLL
26 MHz REF
12
CLOCK
DATA
GAIN
f
F
321.4
MHz