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10 MHz PLL
A11 REFERENCE BLOCK DIAGRAM (ESG-AP & ESG-DP SERIES)
EXT REF
P1-17
FROM:
10 MHz IN
SAMPLER
PULSE GEN
SAMPLING
PHASE DETECTOR
10 MHz OUT OF
LOCK DETECTOR
EXT REF
DETECTION
L_REF_CHANGE
10 MHz DAC
CONTROL
COARSE TUNE
+10V REF
+10V REF
DAC
DAC
FINE TUNE
F
++
--
++
--
CLOSED = EFC LOCK
+3V
EFC CONTROL
CLOSED = EFC OR
EXT REFERENCE
PRESENT
CLOSED = EXT
REFERENCE
PRESENT
L_10MHz_OUT_OF_LOCK
LOOP INTEGRATOR
TUNE
OVEN COLD TIMER
L_OVEN COLD
10 MHz REF
OSCILLATOR
10 MHz
10 MHz
MONITOR
10 MHz OUT
P1-7
TO: 10 MHz OUT
» +7dBm
10 MHz SYNTH
P1-5
TO: FRAC-N/DIVIDER
ASSY
» +7dBm
10 MHz
OK
1 GHz PLL
F
PHASE
DETECTOR
DIVIDE
BY 100
1 GHz
OUT OF LOCK
DETECTOR
CLOSED =
HET BAND
1 GHz
VCO
ABUS
VTUNE
2 T0 4V
ABUS
1_GHZ_DET
ON: 0.05
T0 0.3V
1 GHz REF
P1-19
1 GHZ OUT OF LOCK
10 MHz
TO: OUTPUT
ASSY
BPF
1GHz
1GHz
J3 TO
SAMPLER BD.
sk769b
(MOD1_OPAMP)
EFC LOOP
INTEGRATOR
POWER SUPPLIES
P2-15,30
FILTER
FILTER
FILTER
FILTER
FILTER
5V Reg
5V Reg
10V Reg
12.5 Reg
-12.5 Reg
P2-7
P2-26
P2-6,21
P2-14,29
P2-4,19
P2-2,17
P2-1,16
+32VF
+5V_STBY
+15 SF
+15 VF
+10V REF
+5 VD
-5 VF
-12.5 V
+12.5 V
+5V (PLL)
A
D
FILTER
+3QV
+15V.STBY
+15V
+5.2VD
-5.2V
-15V
ANALOG GROUND
DIGITAL GROUND
DIGITAL INTERFACE
CLK
SELECT
DATA
CLK
DATA
ENABLE/INTRPT
SERIAL I/O
DIGITAL
CONTROL
EEPROM
PARALLEL
LOAD
SHIFT
REG
10 MHz OUT OF LOCK
1GHz OUT OF LOCK
PULSE_ MOD
OVEN_COLD
10 MHz_OK
EXT REF_PRESENT
MOD_1_OVERANGE
MOD_1_UNDERANGE
MOD_2_OVERANGE
MOD_2_UNDERANGE
&
L_OVEN_COLD
L_MOD_LEVEL_INT
&
L_10 MHz_OUT_OF_LOCK
L_1GHz_OUT_OF_LOCK
CLK P2-24
DATA P2-11
ENABLE/INTERRUPT
P2-25
L_EXT_REF_CHANGE
INT 1
INT2
INT3
INT4 (Serial Data)
MOD1_OUT
MOD2_OUT
V TUNE
MOD1_PEAK_OUT
MOD2_PEAK_OUT
LIN_AM_MOD
1 GHz_DET
FM_MOD
P2-9
ABUS
PULSE MOD
PULSE MUX
&
MOD1_OUT
MOD2_OUT
AUD_1
AUD_2
INT_MOD
+5V
-7.5V
COMP
+
COMP
+
-0.6V
PULSE MOD
P3-7
TO: OUTPUT
ASSY
+5V
+5V
BURST PULSE
P3-8
FROM: BASEBAND
GEN ASSY.
MODULATIONS INPUTS
ABUS
ABUS
MOD_1_OUT
MOD_2_OUT
FOR
FUTURE
USE
AUD_1
AUD_2
INT_MOD
P3-5
P3-2
P3-6
FROM: CPU
MOTHERBOARD
MOD_1_OUT
MOD_2_OUT
CLOSED =
DC COUPLED MODULATION
CLOSED =
DC COUPLED MODULATION
MOD LEVEL
DIAGNOSTICS
ABUS
ABUS
MOD1_PEAK_OUT
MOD2_PEAK_OUT
MOD_1_OUT
MOD_2_OUT
L_MOD_LEVEL_INT
MOD_1_OVERANGE
MOD_1_UNDERANGE
MOD_2_OVERANGE
MOD_2_UNDERANGE
EXT_MOD_1
P3-19
FROM: EXT
1 INPUT
EXT_MOD_2
P3-10
FROM: EXT
2 INPUT
LF OUTPUT
DAC
PULSE MUX
MOD1_OUT
MOD2_OUT
AUD_1
AUD_2
INT_MOD
LIN_AM_MOD
FM.MOD
LF OUT
P3-13
TO: LF OUT
SCALE
+
FM MOD
ABUS
FM_MOD
DAC
DAC
DAC
FM2 MUX
FM1 MUX
MOD1_OUT
MOD2_OUT
AUD_1
AUD_2
INT_MOD
MOD1_OUT
MOD2_OUT
AUD_1
AUD_2
INT_MOD
+2VREF
+2VREF
NC
FM_MOD
P3-11
TO: FRAC-N/DIVIDER
ASSY
+10VREF
+10VREF
OFFSET
SCALE
OFFSET
FM
MOD
A11 REFERENCE BLOCK DIAGRAM (ESG-AP & ESG-DP SERIES)
AM MOD
ABUS
LIN_AM_MOD
DAC
AM1 MUX
MOD1_OUT
MOD2_OUT
AUD_1
AUD_2
INT_MOD
+2VREF
NC
DAC
AM2 MUX
MOD1_OUT
MOD2_OUT
AUD_1
AUD_2
INT_MOD
+2V REF
LIN_AM_MOD
P3-17
TO: OUTPUT
ASSY
LIN_AM_MOD