Filter
Top Products
sk784b
ESG-DP SERIES RF BLOCK DIAGRAM (OPTION UND)
ESG-DP SERIES RF BLOCK DIAGRAM (OPTION UND)
H DUAL ARBITRARY WAVEFORM GENERATOR BOARD
CLOCK IN
ARB_REF
Q_OUT
DATA
POL
LATCH
I/O DATA BUS
SWITCH
REFERENCE
PLL_CLOCK
SOCLK 1
SOCLK 1
POL_LATCH
EVENT 1 OUT
EVENT 2 OUT
NSGEND
SQADV
WFCNT
PLL_ON
I/O DATA BUS
Q
RAM
DATA
I
RAM
EXT_CLK
EXT_SYNC
PATTERN_TRG
EXT_DATA
DSP
RAM
MEMORY
RAM
MEMORY
DATA
SEQUENCER
Q
SYNC IN
DATA IN
PATTERN
TRG
CONTROL
LOGIC
SOCLK 0
SOCLK 0
I_OUT
I
LIN_AM_MOD
RPP
G ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RF OUTPUT
F OUTPUT
AUX
OUT
(Coherent
Carrier)
EXT
I INPUT
EXT
Q INPUT
FEED FORWARD AM
PULSE MOD
DETECTOR
SHAPING
BURST
MODULATOR
DRIVER
ALC
MODULATOR
DRIVER
ALC
MODULATOR
BURST
MODULATOR
HOLD ALC
IN_BAND_AM
ALC_REF
DAC
ALC REF
ALC
HOLD
50
ALC
DETECTOR
1 GHz REF
.75-1 GHz
.0-.25 GHz
.25-4 GHz
DAC
QUAD
DAC
VBLO
DAC
DAC
CAL
VOLTAGE
CAL
VOLTAGE
DAC
DAC
I OFFSET
I GAIN
Q GAIN
Q OFFSET
0
90
IQ MODULATOR
2
E DIVIDER (PART OF FRAC-N DIVIDER)
22 2
2-4 GHz
1-2 GHz
.5-1 GHz
.25-.5 GHz
.25-4 GHz
D REFERENCE
LIN_AM_MOD
EXT 1
INPUT
EXT 2
INPUT
10 MHz BW
LF OUT
PULSE MOD
EXT 10 MHz
INPUT
VCO
1 GHz
1 GHZ
REF
1 GHz
100
PLL
10 MHz
10 MHz
SYNTH
10 MHz
OUT
10 MHz
CLK
PLL
J3
C SAMPLER
F
¦
F
¦
S
+ / -
4
750 MHz
J6
P = 8, 9, or 10
f
if
f
s
f
yo
30-70 MHz
750 MHz
600-735 MHz
765-900 MHz
2.93 MHz Steps
6
M
J1
1 GHz In
4 < M < 51
- -
5 < N < 9
- -
f = N * f + f
yo s if
2 P
LO
IF
J3
RF
FRAC-N
256
M
PROGRAMMABLE
DIVIDER
DATA
cw
fm
cw
fm
750 MHz
RF OUT TO
FRAC-N/DIVIDER
B YO DRIVER
J7
J8
RF OUT TO
SAMPLER
P/O
J1
-15V
FM
PRETUNE
DAC
SCALING
CROSS
OVER
FM
COIL
MAIN
COIL
P/O
J1
YO
J4
J3
<115 Hz
4-8 GHz
400-1000
MHz
10 MHz
Paren/Tessera
Frac-N
SYNTH
A FRAC-N (PART OF FRAC-N/DIVIDER)
FM_MOD
DAC
DAC
LIN_BURST
LOG_BURST
BURST_PULSE
BURST_PULSE