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A8 FLEX GENERATOR BLOCK DIAGRAM
REV. C & D (OPTION UN8 & UN9)
A8 FLEX GENERATOR BLOCK DIAGRAM
REV. C & D (OPTION UN8 & UN9)
sk786b
POWER SUPPLY INPUTS
P1-14, 64
+15VF
+5VD
Analog
Common
Digital
Common
P1-16, 17, 66, 67
P1-1, 7, 54, 56
P1-22, 28, 34,
40, 46, 69, 75,
81, 87, 93, 99
TP100
MPU Clock
Configuration "C"
Configuration "B"
Configuration "A"
Data Configuration
Field Programmable
Gate Array "B"
Data Configuration
Field Programmable
Gate Array "A"
Data Configuration
Field Programmable
Gate Array "C"
External RAM
32K X 8 X 2 pages
External RAM
32K X 8 X 2 pages
MPU
Clock
14.7456 MHz
Configuration
Flash 4MB
DRAM
4MB
Boot ROM
Microprocessor
+3.3V to +5V
Conversion
3.3V
Baseband and External I/O
Symbol Sync OutSymbol Sync Out
Burst Pulse
P2-16P2-16
P1-30
P2-14P2-14
P1-31
P2-12P2-12
P1-80
P2-10
P2- 8
Clock OutClock Out
Intl ACL Hold
Data OutData Out
L DCC Alt Pwr Sel
Event 2
Event 1
P2- 6
P2- 4
P2- 2
Ext Alt Power
Ext Pattern Trigger
Ext Burst Gate
P1-16Bit Clock
P3-2Sub I Clock
P1-49
P1-50
P3-100
P3-85
P3-84
Ext Data
Ext Clock
Ext Symbol Sync
Trigger
10 MHz Reference
P4- 2
P4- 4
P4- 6
P4- 8
I Data 0
I Data 1
I Data 2
I Data 3
P4-10
P4-12
P4-14
P4-16
Q Data 0
Q Data 1
Q Data 2
Q Data 3
P3- 6
P3- 8
P3-10
P3-12
P3-14
P3-18
P3-20
Burst Gate
Alt Power
Data
Ext Symbol Sync
Ext Clock
Int/Ext Clock Select
BB Gen Enable
MPU BUS
CPU
Interface
Control
Board
Identification
EEPROM
Data Generator
RAM
8MB X 8
Global Clock
&
Global Input Mux
CPU BUS
UART
162550
Rx Tx
IRQ
and
Status
P1
Motherboard
Digital Card Cage
Connector
Control
Data
Address
Global Clocks and Inputs
FPGA-to-FPGA BUS